The present invention relates, in general, to bonding substrates together, and more particularly, to methods and means for bonding a semiconductor substrate to a support substrate.
An important step in manufacturing semiconductor devices is electrically connecting circuit components in a semiconductor substrate to support substrates such as printed circuit boards, leadframes, or the like. Techniques for forming these electrical connections include wirebonding, tape automated bonding (TAB), and flip-chip bonding. In wirebonding, the semiconductor substrate is typically separated into individual semiconductor die which are mounted to a support substrate such as a printed circuit board. Then, wirebonds are formed between bonding pads on the semiconductor die and corresponding contact pads on the support substrate. Wirebonding techniques are well known and are discussed in, for example, U.S. Pat. No. 5,001,545 issued to Kalfus et al. on Mar. 19, 1991.
In conventional flip-chip bonding, round or hemispheroidal solder bumps are formed on the semiconductor substrate bonding pads. Subsequently, the round or hemispheroidal solder bumps are mated with corresponding bonding pads on a support substrate such as a printed circuit board. Flip-chip bumps and bonding techniques are well known and discussed in for example, U.S. Pat. No. 5,218,234 issued to Thompson et al. on Jun. 8, 1993.
Although wirebonding and conventional flip-chip bonding are useful techniques, each technique has inherent drawbacks. For example, wirebonding to power semiconductor devices built in gallium arsenide (GaAs) wafers requires the GaAs wafers to be thin because they are poor thermal conductors. However, thin GaAs wafers are undesirable because they are brittle and have increased susceptibility to breakage. Further, thinning processes for GaAs wafers creates toxic by-products.
The round or hemispheroidal solder bumps used in flip-chip bonding, on the other hand, form bonds having high stress regions at the interface of the bump and the support substrate, which tends to weaken these bonds. Thermal expansion or contraction of either the semiconductor die or the support substrate further weakens the bond at the high stress region, and may cause the bond to break due to thermal fatigue.
Another drawback to prior art wirebonding and flip-chip bonding techniques is that heat removal from the semiconductor die is accomplished by mounting a heatsink to the backside of the semiconductor die, thereby requiring additional processing steps.
Accordingly, it would be advantageous to have a method and structure of bonding two substrates, wherein the bond is less susceptible to damage caused by stresses associated with the expansion and contraction of the substrates. Further, the method should permit bump formation over active areas of the semiconductor substrate. Moreover, it is desirable for the structure to promote heat removal from a front side of the semiconductor die.